In the semiconductor manufacturing industry diffusion metal oxide semiconductor (DMOS) transistors are commonly used in power integrated circuits. A DMOS transistor comprises a source region and a body region. During the manufacture of a DMOS transistor the source region and the body region are simultaneously diffused so that the channel length of the DMOS transistor is defined by the difference between the two diffusion lengths. The double diffusion feature of the DMOS transistor permits a short channel region to be formed that can control large drain currents by the gate voltage of the DMOS transistor. In a DMOS transistor a drift region is formed between the short channel and the drain of the DMOS transistor.
DMOS transistors are categorized as either vertical DMOS (VDMOS) transistors or lateral DMOS (LDMOS) transistors depending upon the direction of the current path in the transistor. In a lateral DMOS transistor the source region and the drain region are located on approximately the same level of the transistor so that the direction of the current path is generally in a lateral direction.
Undesirable modes of operation may occur in a DMOS transistor. These undesirable modes of operation are generally referred to as “parasitic” modes of operation. These parasitic modes of operation may take the form of an undesirable parasitic bipolar transistor that is formed within the structure of the DMOS transistor. For example, consider the prior art N-type lateral DMOS device 100 that is shown in FIG. 1. N-type lateral DMOS device 100 is designed to be used for inductive full load or half bridge converters. The letters STI in FIG. 1 refer to and designate “shallow trench isolation” structures in the device 100. As shown in FIG. 1, the structure of device 100 forms a parasitic PNP bipolar transistor 110 on the high side of the device 100 and forms a parasitic NPN bipolar transistor 120 of the low side of the device 100.
The parasitic PNP bipolar transistor 110 is formed in the Ndrift region 130 between the P-type body 140 and the P-substrate 150. The presence of this parasitic PNP bipolar transistor 110 can cause latch up problems in the operation of the N-type lateral DMOS device 100.
The parasitic NPN bipolar transistor 120 is formed in the P-substrate 150 between the Ndrift region 130 and the Nwell 160. The presence of this parasitic NPN bipolar transistor 120 can also cause malfunctions in the operation of the N-type lateral DMOS device 100.
One prior art approach to reducing the effect of the presence of the parasitic PNP bipolar transistor 110 is shown in the structure 200 that is shown in FIG. 2. A heavily doped N-type buried layer 210 is formed between the Ndrift region 130 and the P-substrate 150. The heavily doped N-type buried layer 210 forms the base of the parasitic PNP bipolar transistor 110. A heavily doped N-type sinker 220 is provided from a shallow trench isolation (STI) structure down to the N-type buried layer 210. The N-type sinker 220 separates the Ndrift region 130 from a P-type epitaxial layer 230 (P-EPI 230) as shown in FIG. 2.
In order to minimize the beta of the parasitic PNP bipolar transistor 110 it is necessary to have a wide base width and a high doping concentration. However, the width of the N-type buried layer 210 is determined by the diffusion process. This means that it is not possible to simultaneously achieve a wide base width and a high doping concentration. This is illustrated in the structure 300 that is shown FIG. 3. When the width of the N-type buried layer 210 has a relatively small base width (designated with the numeral 310 in FIG. 3) then the peak doping profile is relatively high (designated with the numeral 320 in FIG. 3). When the width of the N-type buried layer 210 has a relatively wide base width (designated with the numeral 330 in FIG. 3) then the peak doping profile is relatively low (designated with the numeral 340 in FIG. 3). This prior art approach has a significant limitation in that it is not possible to achieve both a wide base width and a high doping concentration at the same time.
One prior art approach to reducing the effect of the presence of the parasitic NPN bipolar transistor 120 is shown in the structure 400 that is shown in FIG. 4. A heavily doped N-type guard ring 410 is formed in the P-Substrate 150 as shown in FIG. 4. A P-type region 420 is also formed between the “shallow trench isolation” structures as shown in FIG. 4.
This causes a protection NPN bipolar transistor 430 to be formed between the Ndrift region 130 and N-type guard ring 410. The P-type region 420 provides the base of the protection NPN bipolar transistor 430. The Ndrift region 130 provides the emitter for the protection NPN bipolar transistor 430 and the N-type guard ring 410 provides the collector for the protection NPN bipolar transistor 430.
As the collector of the protection NPN bipolar transistor 430 the N-type guard ring 410 reduces the amount of current that flows from the Nwell 160. However, in spite of the helpful effect of the presence of the protection NPN bipolar transistor 430, the parasitic NPN bipolar transistor 120 still exists. Therefore, there is still some current flowing from the Nwell 160 that contributes to the malfunction of the structure 400 that is shown in FIG. 4. This prior art approach has a significant limitation in that it is not possible to completely stop the current that is due to the presence of the parasitic NPN bipolar transistor 120.
Therefore, there is a need in the art for a system and method that is capable of manufacturing lateral diffusion metal oxide semiconductor (LDMOS) transistors that reduces and minimizes the effect of parasitic bipolar transistors within the lateral diffusion metal oxide semiconductor (LDMOS) transistors.